TMS320F2812PGF

Product Summary

TMS320F2812PGFA absolute maximum ratings: (1)Supply voltage range, VDD, PLLVCCA, VDDO, and VCCA: - 0.3 V to 4.6 V; (2)Supply voltage range, CVDD: - 0.5 V to 2 V; (3)VCCP range: - 0.3 V to 3.6 V; (4)Input voltage range, VIN: - 0.3 V to 4.6 V; (5)Output voltage range, VO: - 0.3 V to 4.6 V; (6)Output voltage range,VO: - 0.3 V to 4.6 V; (7)Input clamp current, IIK (VIN < 0 or VIN > VCC): ± 20 mA; (8)Output clamp current, IOK (VO < 0 or VO > VCC): ± 20 mA; (9)Operating free-air temperature ranges, TA: A version: - 40℃ to 85℃; (10)S version: - 40℃ to 125℃; (11)Junction temperature range, TJ: - 40℃ to 150℃; (12)Storage temperature range, Tstg: - 65℃ to 150℃.

Features

High-Performance Static CMOS Technology ? Clock and System Control
– 150 MHz (6.67-ns Cycle Time) – Dynamic PLL Ratio Changes Supported
– Low-Power (1.8-V Core @135 MHz, – On-Chip Oscillator
1.9-V Core @150 MHz, 3.3-V I/O) Design – Watchdog Timer Module
? JTAG Boundary Scan Support
(1)
? Three External Interrupts
? High-Performance 32-Bit CPU ( TMS320C28x?)
? Peripheral Interrupt Expansion (PIE) Block That
– 16 x 16 and 32 x 32 MAC Operations Supports 45 Peripheral Interrupts
– 16 x 16 Dual MAC ? Three 32-Bit CPU-Timers
– Harvard Bus Architecture ? 128-Bit Security Key/Lock
– Atomic Operations – Protects Flash/ROM/OTP and L0/L1 SARAM
– Fast Interrupt Response and Processing – Prevents Firmware Reverse-Engineering
– Unified Memory Programming Model ? Motor Control Peripherals
– 4M Linear Program/Data Address Reach – Two Event Managers (EVA, EVB)
– Code-Efficient (in C/C++ and Assembly) – Compatible to 240xA Devices
– TMS320F24x/LF240x Processor Source Code ? Serial Port Peripherals
Compatible – Serial Peripheral Interface (SPI)
? On-Chip Memory – Two Serial Communications Interfaces
– Flash Devices: Up to 128K x 16 Flash (SCIs), Standard UART
(Four 8K x 16 and Six 16K x 16 Sectors) – Enhanced Controller Area Network (eCAN)
– ROM Devices: Up to 128K x 16 ROM – Multichannel Buffered Serial Port (McBSP)
– 1K x 16 OTP ROM ? 12-Bit ADC, 16 Channels
– L0 and L1: 2 Blocks of 4K x 16 Each – 2 x 8 Channel Input Multiplexer
Single-Access RAM (SARAM)
– Two Sample-and-Hold
– H0: 1 Block of 8K x 16 SARAM – Single/Simultaneous Conversions
– M0 and M1: 2 Blocks of 1K x 16 Each
– Fast Conversion Rate: 80 ns/12.5 MSPS
SARAM
? Up to 56 General-Purpose I/O (GPIO) Pins
? Boot ROM (4K x 16)
? Advanced Emulation Features
– With Software Boot Modes
– Analysis and Breakpoint Functions
– Standard Math Tables
– Real-Time Debug via Hardware
? External Interface (2812)
? Development Tools Include
– Over 1M x 16 Total Memory
– ANSI C/C++ Compiler/Assembler/Linker
– Programmable Wait States
– Code Composer Studio? IDE
– Programmable Read/Write Strobe Timing
– DSP/BIOS?
– Three Individual Chip Selects
– JTAG Scan Controllers
(1)
? Low-Power Modes and Power Savings
– IDLE, STANDBY, HALT Modes Supported
– Disable Individual Peripheral Clocks

Diagrams